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About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Digital IC Design Senior Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
What You Can Expect
- Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
- Work closely with system and chip architects to design industrial quality implementations.
- Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
- Produce comprehensive block u Architecture and register Specs.
- Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies.
- Supervise or mentor other digital design engineers.
What We're Looking For
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.
- Creating micro-architectural specs from standards, architectural specifications.
- System Verilog RTL coding with System Verilog Assertions.
- Universal Verification Methodology.
- Creating modular/reusable design components.
- Embedded micro-controller systems.
- Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
- Demonstrated success in project leadership.
- Experience in the following areas is a plus: Design for Automotive Safety (ASIL) I2C, SPI, SMBUS.
- Mixed-signal simulation (Cadence AMS).
- Knowledge of power conversions systems.
Expected Base Pay Range (USD)
182,360 - 273,200, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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Marvellについて

Marvell
PublicMarvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.
5,001-10,000
従業員数
Santa Clara
本社所在地
$15.2B
企業価値
レビュー
3.6
10件のレビュー
ワークライフバランス
3.2
報酬
3.8
企業文化
3.5
キャリア
2.8
経営陣
2.9
62%
友人に勧める
良い点
Good benefits and compensation
Supportive team and leadership
Flexible work arrangements
改善点
Limited career advancement opportunities
High workload and long hours
Poor management communication
給与レンジ
16件のデータ
Junior/L3
Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II
1件のレポート
$111,800
年収 総額
基本給
$86,000
ストック
-
ボーナス
-
$111,800
$111,800
面接体験
1件の面接
難易度
3.0
/ 5
期間
14-28週間
内定率
100%
体験
ポジティブ 100%
普通 0%
ネガティブ 0%
面接プロセス
1
Application Review
2
Recruiter Call
3
Technical Screen
4
Final Round Interview
5
Offer Decision
よくある質問
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
UI/UX Design Principles
ニュース&話題
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2d ago
Please don’t rush Marvel’s Spider-Man 3.
The biggest problem with Marvel’s Spider-Man 2 was that it was rushed. It’s still a great game but it had room to be better. I hope insomniac can learn from this and not rush the game. There’s no need to rush it, hype will always be there and we can wait. I really don’t want to hear about a bunch of cut content and go “ah man that would’ve been really cool” just like with Spider-Man 2. I also don’t want to see things featured in previous games missing. I remember reading somewhere about an inter
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Marvell’s AI Story Just Got Stronger With Google — But Is it Too Late to Buy? - 24/7 Wall St.
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News
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2d ago