Job Details:

Job Description:

• The Role and Impact As a DFT Design Engineer, you will play a pivotal role in Intel's product development process, ensuring our products meet the highest standards for quality, performance, and manufacturability. You will lead efforts to implement and optimize Design for Test (DFT) features, contributing significantly to enhancing testability, accelerating production ramp, and improving silicon debug efficiency. Your expertise will directly impact Intel's mission to deliver innovative and cutting-edge technologies that transform industries and enrich lives.

Key Responsibilities:

• Develop and implement logic design, register transfer level (RTL) coding, and simulation for DFT features such as SCAN, MBIST, and BSCAN.
• Collaborate on architectural and microarchitectural definitions for DFT features at block, subsystem, and SoC levels.
• Write, optimize, and integrate RTL and structural code to achieve power, performance, area, timing, and test coverage goals.
• Drive verification of DFT designs, ensuring features are correctly implemented according to architecture and microarchitecture specifications.
• Develop and deliver high-volume manufacturing (HVM) content for rapid silicon bring-up and production ramp on automatic test equipment (ATE).
• Collaborate with post-silicon and manufacturing teams to support silicon debug, verification, and documentation of learnings and improvements.
• Integrate DFT blocks into functional IP and SoC designs, providing high-quality support to SoC customers.
• Ensure high test coverage through structural and specific IP tests to meet quality and defect-per-million (DPM) objectives.

Qualifications:

• Minimum Qualifications
• Bachelor's degree or equivalent in Electrical Engineering, Computer Engineering, or a related field.
• 9+ years of experience with a Bachelor's degree, 6+ years with a Master's degree, or 4+ years with a PhD.
• Proficiency in DFT methodologies and tools, including SCAN, MBIST, and BSCAN.
• Expertise in RTL coding, simulation, and integration for DFT designs.
• Strong knowledge of digital design fundamentals, SoC clocking, and static timing analysis.
• Hands-on experience with EDA tools such as lint tools and timing analysis tools.
• Proven ability to develop HVM content for ATE and optimize designs for test coverage and production efficiency.

Preferred Qualifications:

• Demonstrated ability to collaborate across teams to solve complex problems and achieve shared objectives.
• Strong communication skills with the ability to articulate technical concepts clearly and effectively.
• Experience supporting post-silicon debug and manufacturing processes. Join Intel and make a lasting impact on the future of technology. Apply today to become a key contributor to our mission of delivering world-changing innovation.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.