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Job Details:
Job Description:
Intel is a global leader in technology innovation, dedicated to creating products that transform industries and improve lives worldwide. We design and manufacture advanced silicon solutions that power the digital world. Our commitment to excellence drives us to push the boundaries of technology and deliver cutting-edge solutions that meet the needs of our customers. If you are passionate about innovation and eager to contribute to transformative projects, Intel is the place for you.
Join us at Intel and be a part of a team that is shaping the future of power delivery technology.
The role’s responsibilities include but are not limited to:
- Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
- Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
- Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
- Replicates, root causes, and debugs issues in the presilicon environment.
- Finds and implements corrective measures to resolve failing tests.
- Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
Qualifications:
You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience - OR -
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience
- Experience in Digital logic experience.
- Experience in VHDL/Verilog/System Verilog.
- Experience in Testbench component development (preferably in OVM/UVM), and design debugging skills.
Preferred Qualifications:
- 7+ years of related experience
- Analog debug skills
- Real number (current, voltage) simulation modeling and debug skills
Relevant experience can be obtained through schoolwork, classes, and project work, internships, military training and/or work experience.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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About Intel

Intel
PublicIntel inside.
120,000+
Employees
Santa Clara
Headquarters
$200B
Valuation
Reviews
3.5
3 reviews
Work Life Balance
3.0
Compensation
3.0
Culture
2.5
Career
2.5
Management
2.0
25%
Recommend to a Friend
Pros
Offers internship opportunities
Interview opportunities available
Cons
Major job cuts and layoffs
Spam emails after rejection
Poor communication practices
Salary Ranges
6 data points
Senior/L5
Senior/L5 · Advanced Field Service Engineering Data Analyst
1 reports
$132,904
total / year
Base
$102,234
Stock
-
Bonus
-
$132,904
$132,904
Interview Experience
2 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
System Design
Past Experience
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