Fullchip Floorplan Design Engineer at Intel

Job Details:

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

We are looking for a talented and motivated Physical Design Floorplanning Engineer to join our team.

In this role key responsibilities are:

• Top-down SoC Floorplan activities like best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, multi-power domain planning, pin-cutting, bump-planning by working with package/platform.
• Estimate die-area and define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from different product family.
• Drive execution and supervise progress of smaller blocks or sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule.
• Plan short and long-term work schedule, understanding dependencies between different domains like top, block place and route.

Responsibilities:

• Collaborate with other stake holders like the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power.
• Experienced in industry standard tools.
• Help drive methodologies, tools and best-known methods to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

Bachelor in Electrical/Electronics/Computer Engineering with 3+ years of relevant experience or Master's degree in Electrical/Electronics/Computer Engineering with 2+ years of relevant experience.

• 2+ years of experience using industry-standard EDA tools for floorplanning and APR.
• 1+ years of experience with multi-power domain designs.
• 1+ years of experience with Synopsys Fusion Compiler.
• 3+ years of experience with TCL, Python or Perl programming.
• 2+ years of experience with Calibre or ICV verification.

Preferred Qualifications:

• Good Knowledge with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, Global signal planning, I/O planning and Macro placement.
• Familiar with hierarchical design approach, top-down design, handling MIB (multiple instantiation blocks), routing and physical convergence.
• Deep knowledge of SoC Floorplan requirements like multiple voltage and clock domains, Level Shifters/Isolation, thermal management, Die-to-Die interconnects, and package interactions.
• Understanding of UPF/CPF, low power static verification, and multi-power domain design planning.
• Expertise with Floorplanning tools
• ICC2/FC, Place and Rout flows, and Physical Design Verification Flows is required.
• Experience with large subsystem designs (20M gates) with frequencies in excess of 2GHz.
• Good automation skills/focus with coding familiarity in tcl/perl/python
• Excellent communication and teamwork skills

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Colorado, Fort Collins

Additional Locations:

US, California, Folsom, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 05/22/2026

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.