Job Details:

Job Description:

• Architect, design, develop, and validate power management p Code for IPs and So Cs.

• Develops and implements power management features and algorithms to manage the SoC and platform with clear partitioning on firmware and hardware. Collaborates on silicon architecture definition and develops the power management microarchitecture specification, presilicon verification test plans, and performs functional verifications as per specifications.

• Develop IP Unit models and definition of verification infrastructure and related TFMs needed for power management verification.

• Conducts power and performance analysis and optimization to meet postsilicon performance goals until product PRQ/PRT, working in collaboration with PnP teams.

• Provide recommendations for future power management architectures. Influence hardware, OS, and platform designs to meet the power performance criteria.

• Develops methodologies and models to drive continuous improvements in developing and validating power management flows, features, and algorithms.

• May also research and adopt machine learning and other AI applications to improve performance and user experience.

Qualifications:

• Prior Experience in SoC development / Embedded systems is mandatory.

• Exposure to CPU, Graphics, Media, Display, DDR, Imaging, Audio, IO systems is highly desired with strong expertise in any of these domains.

• Minimum 5 years of experience in SoC/Embedded Systems with at least 5+ years of firmware/software validation experience dealing with hardware level intricacies.

• Proficient in Assembly programming/C/C++ and in a microcontroller environment (Tensilica/ARC/ARM Cortex M or similar).

• Close interactions with multiple Performance/Compute critical IP to understand their Power management requirements, translating them to cutting edge algorithms for best-in-class Leakage/Dynamic power numbers

• Knowledge of two or more power management features and functionality, including: power states/flows, power consumption, power delivery, reset sequence, OS power management, device power management and stability between power management subsystem/domains and other subsystems in the System setting

• SW/HW Validation Experiences: unit / functional/ integration / exploratory

• Debugging techniques local/remote, including profilers, debuggers, and system monitoring hardware desired.

• Excellent written and verbal communication skills.

• Should have worked in cross-functional teams and demonstrated experience in root cause analysis

• Ability to learn new skills quickly and independently.

• Excellent written and verbal communication skills.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.