Analog Layout Design Engineer at Intel

Job Details:

Job Description:

Job Summary We are seeking an Entry Level Analog Layout Engineer for a time bound assignment to support analog and mixed signal IP development. The engineer will work as an individual contributor, under the guidance of senior layout and circuit designers, executing custom layout implementation and physical verification tasks for analog blocks used in SoC and IP designs. ________________________________________ Key Responsibilities • Perform analog and custom layout design for assigned blocks under supervision • Implement layouts using Virtuoso / Custom Compiler or equivalent tools • Run and debug physical verification checks, including: o DRC, LVS o Density and reliability checks o EM/IR (Red Hawk / Totem or equivalent) o ESD and Latch up checks (as applicable) • Follow layout constraints provided by circuit designers and layout leads • Support layout iterations, ECOs, and signoff closure • Adhere to established methodologies, checklists, and quality standards • Document layout issues and support reviews with senior engineers

Qualifications:

• Bachelor's degree (B.Tech) in Electrical Engineering, Electronics Engineering, or related field • 0-2 years of experience or strong academic exposure in Analog / Custom Layout Design • Basic understanding of: o Analog layout practices and matching concepts o Layout vs schematic consistency o Reliability and manufacturability considerations • Familiarity with custom layout tools and physical verification flows • Ability to work as an individual contributor under technical guidance • Strong attention to detail and willingness to learn ________________________________________ Preferred Qualifications • Hands on exposure to Virtuoso / Custom Compiler • Experience running Calibre / ICV for DRC, LVS, and density checks • Exposure to Red Hawk / Totem for EM/IR analysis • Academic projects or internships in analog / mixed signal design or layout • Understanding of basic analog circuits (e.g., op amps, drivers, IO cells) • Scripting exposure (SKILL, Tcl, Python) is a plus

Job Type:

Intel Contract Employee:

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.