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职位Intel

Post-silicon Validation and Debug Engineer

Intel

Post-silicon Validation and Debug Engineer

Intel

US

·

On-site

·

Full-time

·

1w ago

Job Details:

Job Description:

The Role and Impact

As a SoC Debug Engineer, you will play a pivotal role in ensuring Intel's cutting-edge products perform seamlessly, innovating at the intersection of hardware, firmware, and software. Join our team to shape the future of technology by driving exceptional system-on-chip (SoC) debug solutions, improving industry workflows, and defining strategies that contribute to Intel's global leadership in innovation.

This position offers an exciting opportunity to collaborate with cross-disciplinary teams, influence technical direction across Intel, and develop solutions fundamental to delivering high-quality products to market.

Key Responsibilities

  • Perform low-level and complex debug across multiple systems, subsystems, or SoC levels for Intel products.

  • Develop validation plans and execute tests for multiple domain- and system-level features/flows in the SoC.

  • Develop and implement techniques for faster SoC and platform-level debug while isolating failing system components.

  • Utilize design-for-debug (DFD) tools and scripts to continuously improve debug discipline.

  • Conduct root cause analysis, resolve triage failures and marginality issues, and track SoC debug progress.

  • Collaborate with design, system validation teams, and high-volume manufacturing factories to characterize new device features and functionalities.

Qualifications:

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

  • 0-1+ years of experience with a Bachelor's degree or 0 years with a Master's degree in SoC design and debug or equivalent experience.

  • Proficiency in SoC design, architecture, and debug techniques, including DFD tools and methodologies.

  • Strong understanding of firmware and software integration in hardware systems.

  • Ability to apply debug workflows using advanced test methodologies and failure isolation techniques.

Preferred Qualifications

  • Master's degree in Electrical Engineering, Computer Engineering, or related disciplines.

  • Exposure to collaborating across design and validation teams to achieve debug readiness.

  • Familiarity with Graphics and Power Management flows in an SoC design.

  • Drive to influence technical strategies and align organizational goals with technical vision.

We invite you to apply and become part of a team that values innovation, collaboration, and technical excellence. Join us in driving forward Intel's mission to deliver world-class products that shape the future of technology.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, California, Folsom

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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关于Intel

Intel

Intel

Public

Intel Corporation is an American multinational technology company headquartered in Santa Clara, California. It designs, manufactures, and sells computer components such as central processing units (CPUs) and related products for business and consumer markets.

120,000+

员工数

Santa Clara

总部位置

$200B

企业估值

评价

2.7

1条评价

工作生活平衡

3.0

薪酬

3.5

企业文化

3.5

职业发展

2.5

管理层

2.5

25%

推荐给朋友

优点

Company culture

Benefits package

Good communications about culture

缺点

Poor rejection process

Spam emails to candidates

Frustrating candidate experience

薪资范围

16个数据点

Senior/L5

Senior/L5 · Advanced Field Service Engineering Data Analyst

1份报告

$132,904

年薪总额

基本工资

$102,234

股票

-

奖金

-

$132,904

$132,904

面试经验

2次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

常见问题

Coding/Algorithm

Technical Knowledge

Behavioral/STAR

System Design