Job Details:

Job Description:

Candidate will be part of Power delivery team and will work on next generation Xeon Server SoC design. In this role, candidate will be responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off. Responsibilities include but are not limited to the following:

• Must have Experience in Block level/Full chip level EM/IR, PDN analysis.
• Signal EM and Power EM Signoff analysis.
• Development and validation of the PG Grid spec for different high performance SOCs.
• ESD analysis and Signoff for High Performance complex SOCs.
• Validating the IR Drops using Static IR , Dynamic IR Vless and VCD Checks for validating Die and Pkg Components of IR Drops.
• Working with SOC and Packaging Teams on Bumps Assignments, RDL Enablement, Pkg Routing optimizations to improve overall PDN Design.
• Good knowledge on PD would be helpful.
• Perl, TCL Scripting Skills.

Qualifications:

• Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering or related areas.
• At least 8+ years of experience in in Block level/Full chip level EM/IR, PDN analysis.
• Hands - on experience in PDN Signoff using Redhawk, RHSC, Voltus at block level and SOC Level.
• Good understanding on Power Integrity Signoff Checks.
• Proficient in scripting languages (Tcl, Perl, Python).
• Familiarity with Innovus for RDL and Bump Planning.
• Ability to communicate effectively with multiple global cross-functional teams.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.