SoC Debug Engineer at Intel

Job Details:

Job Description:

This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.

Join a highly skilled silicon debug solution organization responsible for developing, maintaining, and supporting a proprietary JTAG-based debug tool used across a major high tech hardware company. Our tool is integral to bringing up, validating, and debugging cutting-edge microprocessors and So Cs. We serve pre- and post-silicon, validation and debug teams worldwide.

Position Overview

We are seeking an early-career FPGA Developer interested in RTL design and verification (VHDL/Verilog/System Verilog). In this role, you will contribute to FPGA-based features that support and extend our proprietary JTAG-based debug tool. You'll work with experienced engineers who will provide mentorship as you learn our architecture, development flow, and lab bring-up practices.

This is an opportunity to grow your FPGA skills at the intersection of silicon validation and debug technology while delivering improvements that help teams debug and validate cutting-edge microprocessors and So Cs.

Key Responsibilities

• Implement and maintain FPGA RTL (VHDL/Verilog/System Verilog) under guidance to enable and enhance debug/validation capabilities.
• Assist with integrating FPGA designs with JTAG/TAP interfaces and debug transport/control logic.
• Write and run simulations; help develop testbenches and automated checks to validate functional correctness.
• Debug RTL and hardware issues using waveforms, assertions, and on-hardware instrumentation (e.g., ILA/Signal Tap) with support from the team.
• Contribute to FPGA build flows (synthesis/place-and-route/bitstream) and help improve reproducibility and resource utilization.
• Collaborate with software, validation, and hardware teams to clarify requirements, implement changes, and support internal users.

Behavioral traits

• Foundational debug skills and a willingness to learn: willingness to investigate issues using simulation, waveforms, and structured troubleshooting.
• Communication skills and willingness to collaborate with cross-functional teams.

Additional Opportunities

• Build FPGA-based test and demo environments to accelerate validation, debug, and internal enablement.
• Contribute to automation around FPGA builds, regression testing, and lab workflows (e.g., scripting, CI, environment setup).

Why Join Us?

• Work on a proprietary debug tool used at massive scale across a world-class hardware organization.
• Solve complex, meaningful problems at the intersection of FPGA, software, and silicon validation.
• Influence infrastructure that directly impacts silicon bring up and validation velocity.
• Grow your skills alongside highly experienced engineers in a collaborative environment.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electronics Engineering, or a related field. A minimum of 2 years of experience is required for candidates with a Bachelor’s degree, while no prior experience is required for candidates with a Master’s degree.

• Experience mentioned above should be in the following areas:

• FPGA/RTL development (including internships, co-ops, or substantial academic/personal projects).

• VHDL and/or Verilog/System Verilog (ability to read, modify, and write RTL).

• Advance English level.

• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications:

• Git and basic software development practices (branching, reviews, documentation).
• Exposure to FPGA vendor toolchains (e.g., Xilinx Vivado, Intel Quartus) and constraints (XDC/SDC).
• Exposure to RTL verification concepts (testbenches, assertions/SVA; UVM familiarity is a plus).
• Familiarity with JTAG/TAP, boundary scan, and debug/bring-up flows.
• Experience debugging FPGA designs in hardware (e.g., ILA/Signal Tap) is a plus.
• Basic scripting (Python/Tcl/Bash) for automation and tooling integration is a plus.
• Interest or exposure to CI/regression practices for hardware/FPGA flows is a plus.
• Understanding of clock-domain crossing, reset strategy, and timing/performance tradeoffs is a plus.
• Familiarity with common interfaces (e.g., AXI, PCIe, Ethernet) is a plus.
• Interest in lab bring-up/validation and working with hardware teams.

If you are passionate about innovation, thrive in collaborative environments, and seek to make a meaningful impact on the future of technology, we encourage you to apply today.

Job Type:

Experienced Hire

Shift:

Shift 1 (Mexico)

Primary Location:

Mexico, Guadalajara

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.