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Job Details:
Job Description:
Designs, develops, and executes power and performance plans for IPs and So Cs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency.
In this position, you will be a member of the Data Center Design Power and Performance (DCD PnP) team. This team is responsible for projecting and optimizing the power, binsplit, thermals, and power-limited performance for Data Center products including Xeon, Xeon-D, and Atom-based So Cs. We offer exciting opportunities to develop technical depth and leadership.
Role responsibilities include, but are not limited to:
- Lead pre-silicon So
C Power projections for a Data Center product:
- Identify and drive power and thermal optimizations to meet SOC PnP goals
- Build and maintain a power model using: architectural, design, and process specifications; historical power data; and current generation power estimates
- Define segment-specific workloads for power and thermal specifications
- Influence product definition starting from Pathfinding and Technology Readiness
- Set workload-based power targets for IPs and So Cs that support the market requirements and drive teams to meet these goals
- Deliver power data to partners to enable power delivery design, thermal modeling, and performance optimization
- Audit power estimate quality from IP and SoC teams
- Drive improvements to IP and SOC PnP methodology
- Participate in SKU definition to match PnP capabilities with manufacturing and marketing needs
- Collaborate worldwide with DCD PnP and cross-functional partner teams including SOC and IP Design, Architecture, Performance, Power Management, Power Delivery, Marketing, Planning, and Process
Qualifications:
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Requirements:
-
The candidate must have a Bachelor's degree Electrical/Computer Engineering and 6+ years of experience or an equivalent combination of education and experience.
-
The ideal candidate's technical skills and experience will include:
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Pre-Si power analysis and modeling
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Power-aware design and identification of architectural, logical, and physical power reduction opportunities
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Understanding of power/performance trade-offs and optimizations
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Experience with industry-standard power estimation tools and Intel's design environment
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Programming or scripting, preferably in perl, python, or TCL
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Knowledge of general computer architecture and silicon concepts
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Thermal modeling and thermal spec for So Cs
Preferred Qualifications:
-
Skilled in effective communication, leadership, and teamwork
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Analytically-driven with strong problem-solving abilities
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A resourceful and disciplined self-starter
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Thorough and detail-oriented
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro
Business group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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About Intel

Intel
PublicIntel inside.
120,000+
Employees
Santa Clara
Headquarters
$200B
Valuation
Reviews
3.5
3 reviews
Work Life Balance
3.0
Compensation
3.0
Culture
2.5
Career
2.5
Management
2.0
25%
Recommend to a Friend
Pros
Offers internship opportunities
Interview opportunities available
Cons
Major job cuts and layoffs
Spam emails after rejection
Poor communication practices
Salary Ranges
6 data points
Senior/L5
Senior/L5 · Advanced Field Service Engineering Data Analyst
1 reports
$132,904
total / year
Base
$102,234
Stock
-
Bonus
-
$132,904
$132,904
Interview Experience
2 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
System Design
Past Experience
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