Integrated Circuit Package Design Engineer at Google

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

We are creating custom-designed silicon to meet Google's growing need for computing power. Our challenges are specific that we can't rely on off the shelf hardware. We design and create the hardware, software, and networking technologies that drive all of Google's services.

As a Silicon Engineer, you will play a crucial role in designing and building the chips and systems at the core of the world's biggest and most powerful computing infrastructure.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Execute physical package substrate design of large form-factor packages for ML High-Performance Computers (HPCs).

• Develop and implement the methodology and CAD flow for substrate design and enhanced productivity.

• Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.

• Collaborate with Signal Integrity (SI)/Power Integrity (PI), thermal, and mechanical engineering teams to refine and enhance product package designs, test vehicles, and mock-up designs for product feasibility.

• Define and document the requirements for the package substrate design and Bill of Materials (BOM).

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 5 years industry experience in chip package design/layout using Cadence Advanced Package Designer (APD) and Mentor Expedition.

• Experience in chip package substrate designs, layout, optimization, design verification, DFM and taping out for production.

• Experience in design automation and scripting.

Preferred qualifications

• Experience in 2.5D/3.5D advanced package design.

• Experience in working with cross functional teams including chip design, SI/PI, and PCB design teams.

• Experience in physical verification flow (e.g., LVS, DRC, connectivity).

• Experience with CAD for creating mechanical drawings, such as Package Outline Drawings(POD).

• Ability to write scripts to customize elements of the Cadence or Mentor workflow.