System Modelling Engineer at Intel

Job Details:

Job Description:

The Role and Impact: As an Analog and Mixed Signal IP Architect, you will play a pivotal role in shaping the future of Intel's cutting-edge technologies. You will be responsible for driving innovative architectures and algorithms that define the next generation of System-on-Chip (SoC) independent analog and mixed signal IPs. We are seeking an experienced Ser Des PHY System Modeling Engineer to lead and support the architecture, modeling, and performance analysis of 224Gbps Ser Des IP. This role focuses on endtoend PHY system modeling, including electrical channel, transmitter (TX), receiver (RX), equalization strategies, clocking, and jitter/noise analysis, enabling robust silicon implementation for nextgeneration ASICs and So Cs. Key Responsibilities: System Architecture and Modeling: Develop endtoend behavioral models for 224Gbps Ser Des PHYs across TX, channel, and RX. Build statistical and timedomain system models to evaluate BER, eye margins, and link robustness Define PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss) Model and optimize PAM4 signaling at very high data rates Channel and Equalization Analysis: Model electrical channels including packages, PCBs, connectors, and crosstalk. Develop and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms Perform Swept channel analysis to ensure compliance across worstcase conditions Support cooptimization of channel, package, and PHY architecture Clocking, Jitter and Noise Analysis: Model PLL/DLL behavior, phase noise, and jitter transfer functions Perform jitter decomposition (RJ, DJ, PJ, SJ) and bathtub curve analysis Analyze CDR performance, loop dynamics, and tolerance to jitter/noise sources Compliance and Standards Support: Support modeling and interpretation of industry standards (IEEE, OIF, etc.), including 224Grelated efforts Define channel and compliance test methodologies Align system models with compliance test specifications and silicon validation strategies Work closely with circuit designers, DSP/algorithm teams, package/PCB engineers, and validation teams Translate systemlevel requirements into blocklevel and circuitlevel specs Support silicon bringup and debug through correlation of lab data with system models

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field, and 12+ years of relevant experience; or Master's degree and 8+ years of relevant experience; or PhD and 4+ years of relevant experience.
• Proficiency in analog circuit design, including TX/RX blocks and system-level understanding.
• Expertise in architecture modeling and high-speed design techniques.
• Demonstrated ability to model, simulate, and optimize performance, power, and area for analog and mixed signal IPs.

Preferred Qualifications:

• Strong leadership and collaboration skills with experience in influencing cross-functional technology roadmaps.
• Solid analytical and problem-solving abilities with a track record of delivering innovative solutions.
• Effective communication skills to articulate architectural features and tradeoffs to design teams and stakeholders.
• A passion for advancing technology and contributing to Intel's mission of innovation and excellence.

Take the next step in your career by applying today. Join us in shaping the future of analog and mixed signal IP and making a lasting impact on the semiconductor industry.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.