Senior Design Lead

Job Summary

To perform verification of High Performance Controller IPs such as, PCIe, UCIe, LPDDR, UAL (Ethernet)

Key Responsibilities

1. Develop verification plans

2. Develop test bench including assertions, checkers, functional coverage etc

3. Develop tests, simulate, debug failures

4. Create defect reports and track to closure

5. Coverage closure and verification sign off

Skill Requirements

System Verilog

UVM

IP verification

Good English communication:

Customer interfacing

Other Requirements

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