Senior Technical Architect

Job Summary

• 14 – 16 years of relevant industry experience in Analog/Mixed-Signal Layout Design.

• Experience and Deep Expertise in one or more of the following domains:

• Power Management

• Data Converters

• High-Speed Analog

• IO Layout

• Clocking Solutions

• Custom IP Development.

Key Responsibilities

• Guide and mentor a team of layout designers to improve productivity, design reviews, and layout methodologies across different projects

• Lead top-level floorplanning, micro-architecture planning, signal/power routing for complex analog blocks (e.g., PLL, ADC, DAC, SERDES) and ensure first-pass silicon success

• Perform and oversee full-custom layout designs, ensuring optimal matching, shielding, and reduction of parasitic effects.

• Drive physical verification, including DRC, LVS, ERC, ESD, Latch-up, and EM/IR drop, to meet strict manufacturing constraints.

• Drive Value Creation initiatives across different layout projects owned.

Skill Requirements

Process Nodes Experience

Hands-on experience in one or more of the following technologies is preferred:

• Intel Advanced Nodes

• TSMC N16 / N7 / N5 / N3

• Samsung Advanced Process Nodes

• Global Foundries Technologies

• Any BCD or Bi-CMOS process nodes.

Other Requirements

Scripting

• Basic programming or scripting skills in one of the below programming languages is highly preferred

• SKILL / SHELL / PERL / TCL

EDA Tools

• Layout Editor: Cadence Virtuoso / Synopsys Custom Compiler

• Physical Verifications: Calibre / PVS / Assura / ICV

• Reliability:

• EM-IR: Voltus / Totem / m Power

• ESD: PERC

Education

• B.Tech / M.Tech in Electrical or Electronics Engineering.