Senior Technical Architect - Silicon Platform Validation, Python

Job Summary

This role is accountable for providing advanced proficiency in RTL Design within complex semiconductor projects. The individual ensures technical excellence by guiding teams in design implementation, optimizing quality assurance, and driving best practices. They play a pivotal role in enabling successful delivery of high-performance design solutions, while actively participating in technical consultations and process compliance.

Key Responsibilities

1. Provide advanced proficiency in RTL Design using Verilog/VHDL by mentoring team members in synthesizable coding practices, module partitioning, and timing closure optimization for complex digital systems.

2. Oversee quality assurance and performance optimization by implementing simulation and verification processes with EDA tools such as Synopsys Design Compiler and Cadence Genus, ensuring adherence to project standards and delivery timelines.

3. Conduct technical feasibility studies and participate in architecture reviews by analyzing RTL alternatives, assessing design risks, and supporting estimation for component breakdown using industry-standard methodologies.

4. Collaborate with project stakeholders using project management tools to define scope, objectives, and deliverables; prepare technical status reports to facilitate issue resolution and project closure.

Skill Requirements

1. Advanced proficiency in RTL Design with Verilog/VHDL for digital logic implementation and optimization.

2. Solid understanding of simulation, synthesis, and verification flows using EDA tools (e.g., Synopsys, Cadence).

3. In-depth knowledge of quality assurance, timing analysis, and best practices in RTL coding.

4. Experience in technical feasibility analysis, design partitioning, and risk assessment.

5. Competence in communicating technical status and collaborating within project teams.

Other Requirements

1. Optional but valuable: Certification in VLSI Design or equivalent (e.g., IEEE Certified VLSI Professional, Cadence Certified RTL Designer).