ET - Senior Group Technical Architect

Job Summary

Experince 20+ years
Perform end‑to‑end physical design flow:
Floorplanning
Power planning (PG grid, IR)
Placement & optimization
CTS (Clock Tree Synthesis)
Routing
Post‑route optimization
Achieve timing closure across all modes and corners
Resolve DRC, LVS, ERC and signoff violations
Handle low‑power design techniques:
Multi‑Vt, Multi‑voltage (UPF)
Power gating, clock gating
Perform physical verification and signoff:
STA (Primetime)
SI / Crosstalk
IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
Collaborate with:
RTL & Micro‑architecture teams

DFT & Test engineers:

Foundry and CAD teams:

Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)

Key Responsibilities

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Skill Requirements

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Other Requirements

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