HCL Technologies
HCL Technologies

Senior Design Lead - Design Validation

RoleEngineering
LevelSenior
LocationChennai, India
WorkOn-site
TypeFull-time
Posted1 month ago
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About the role

Job Summary

Define ASIC/SoC verification strategy
Full chip testplan development

Full chip TB Architecture definition:

UVM based testbench development
SV functional coverage, Assertions coding
C based TB development
Test case development, coding, execution, bug analysis

Gate Level Simulation:

Regressions, coverage analysis
participate in verification closure

Key Responsibilities

Good understanding of ASIC/SoC life cycle
Has participated in multiple ASIC/SoC verification till tapeout stage
Experience writing ASIC/SoC testplans
"1.Experience in ASIC/So

C Testbench definition:

2.Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)."
"1.Expertise & hands-on experience in OVM/UVM methodologies using SV
2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
"1. Experience in developing TB components for SOC with C, SV
"
"1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experince in SOC C based tests coding & debugging"
"Experience in Gate level simulation & netlist debugging
"
"Exeprince in regression failure analayiss
Functioncal and Code Coverage closure"

Experience in Perl/Shell scripting:

Skill Requirements

Languages: Proficiency in Verilog, System Verilog, and core concepts of UVM.
Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.

EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens Questa Sim, Cadence Xcelium/Verdi).
"Protocols:

Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

Other Requirements

Education Degree:

" Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),
Electrical Engineering (EE), VLSI Design, or a closely related field"

Benefits and perks

Learning Budget

About HCL Technologies

Chennai

Headquarters