Technical Lead - Silicon Platform Validation, Python

Job Summary

This role is responsible for leading the conceptualization, design, and delivery of advanced memory layout solutions for products and projects. The individual drives technical excellence by leveraging deep expertise in memory design, guiding teams through complex challenges, and implementing industry-leading practices to ensure solutions are innovative, robust, and aligned with evolving technology standards. They serve as a trusted advisor for clients, contribute to competency development, and play a key role in shaping the organization's technical direction in the domain.

Key Responsibilities

1. Lead memory layout design using advanced EDA tools to architect efficient and reliable memory subsystems, ensuring optimal performance and compliance with client requirements.
2. Oversee team development and implementation of memory solutions, providing expert guidance in SRAM, DRAM, and Flash memory design methodologies.
3. Serve as the subject matter expert in memory architecture, supporting solution delivery and addressing complex technical queries across project teams.
4. Evaluate and integrate new memory technologies and standards, ensuring design practices remain current and deliver high-quality results.
5. Conduct technical interviews, training sessions, and mentorship programs to cultivate a strong pool of memory design professionals within the team.
6. Gather client specifications and translate them into tailored memory solutions using industry-standard design flows and verification techniques.
7. Develop technical whitepapers, collaterals, and market trend analyses to support competency growth and thought leadership in memory layout design.
8. Recommend and implement best practices and client value creation initiatives, leveraging insights from market research and benchmarking.

Skill Requirements

1. Expert proficiency in memory layout design and architecture, including SRAM, DRAM, and Flash technologies.
2. Excellent knowledge of EDA tools such as Cadence, Synopsys, and Mentor Graphics for schematic capture, layout, and verification.
3. Advanced proficiency in physical design, floorplanning, and timing analysis for memory subsystems.
4. Solid understanding of semiconductor fabrication processes and DRC/LVS methodologies.
5. Strong experience in technical leadership, mentoring, and competency development.
6. Excellent communication skills for client interaction and technical documentation.

Other Requirements

1. Certification in VLSI Design or Semiconductor Design (optional but valuable)
2. Synopsys Certified Memory Design Expert or equivalent (optional but valuable)