Senior Technical Architect - Design Validation

Job Summary

15 years of experience in Design verification

Key Responsibilities

• Develop and review C-based tests / reference models integrated with SV/UVM environments
• Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
• Test planning, execution, and closure at IP level
• Writing and debugging constraint-random tests
• Development and analysis of functional coverage and code coverage

Skill Requirements

o Experience in Subsystem verification with CPU driven tests
o Experience in RISC-V based CPU environment
o ARM system IP and debug IP experience

• ASIC IP-level verification using System Verilog and UVM
• Strong Debugging Skills

Other Requirements

null