Senior RTL Design Lead

Job Summary

Candidates with 5 to 7 years experience is mandatory

Experience in Full chip RTL integration is preferred

Experience with ASIC/SoC development flow including synthesis/timing constraints development,

Static Timing Analysis closure, resolving P& R congestion issues etc.

Experience in RTL Synthesis:

Scripting experience

Experience integrating IP's like PCIe, USB, Ethernet etc.

Should be able to lead a team of 2 to 3 Entry Level engineers

Key Responsibilities

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Skill Requirements

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Other Requirements

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