Senior Test Lead - Design Validation

Job Summary

strong RTL Design Verification engineers to perform** block-level verification of IP components**. The role involves validating functionality of IPs provided and ensuring readiness for SoC-level integration.

Key Responsibilities

• Perform RTL design verification for IP blocks such as:

• FSM (Finite State Machine)

• DAC-related logic (with model interaction)

• Pattern memory / controller logic

• Develop and execute comprehensive verification plans

• Build testbenches and verification environments (directed + random testing)

• Validate functional correctness and interface behaviour

• Perform debug and root cause analysis of RTL issues

• Ensure coverage closure and verification completeness

• Work closely with PD and integration teams to enable smooth SoC integration

Skill Requirements

Core Skills

• Strong experience in RTL Design Verification

• Good understanding of:

• Digital design fundamentals

• FSM-based architectures

• IP/block-level verification

Verification Expertise

• Testbench development

• Functional verification methodologies

• Debugging and RTL issue analysis

Programming / Tools

• Working knowledge of:

• System Verilog / Verilog

• UVM or similar verification methodologies (preferred)

• Scripting (Python/Shell – good to have)

Other Requirements

• Ability to work with partially verified / early-stage IP

• Experience handling multiple instances / scalable verification flows

• Strong analytical and debugging skills