Senior Design Lead
About the role
Job Summary
Experience: 5+ years
Experience with Formal Equivalence Verification (FEV) tools is a must
Execute RTL ↔ Netlist, Netlist ↔ Netlist, and ECO FEV at block and full-chip levels
Debug and resolve non-equivalence failures, aborted points, and compare issues due to synthesis, ECO, scan, and DFT logic
Create and maintain reference FEV flows and testcases to validate tool features and methodologies
Develop and automate workflows to improve efficiency and runtime of FEV signoff. Automation using Python/ Perl/Tcl is preferred
Work closely with RTL, Synthesis, DFT, and Physical Design teams for issue closure.
Generate signoff-ready reports and ensure adherence to project signoff criteria
Write clear documentation for FEV flows and train users on tool usage and best practices
Key Responsibilities
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Skill Requirements
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Other Requirements
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Benefits and perks
•Learning Budget
About HCL Technologies
Bangalore
Headquarters