About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation So Cs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed IOs, Analog DFT).

• Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.

• Integrate DFT logic, boundary scan, scan chains, DFT compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.

• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

• Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.

Minimum qualifications

• Bachelor's degree in Electrical, Electronics, Communication, Computer Engineering, a related field, or equivalent practical experience.

• 8 years of experience with implementation and validation of various DFT technologies.

• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.

• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.

• Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications

• Master's degree in Electrical Engineering, or a related field.

• Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).

• Experience in SoC cycles, including silicon bring-up and silicon debug activities.

• Experience in fault modeling.