About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a CMOS Technologist and Foundry Engineer, you'll be part of the growing chip design team. In this role, you'll be responsible for driving CMOS (Complementary Metal Oxide Semiconductor) foundry partners, Intellectual Property (IP), and chip design and implementation teams to perform CMOS transistor scaling and Power/Performance Analysis (PPA), and producing technology roadmap benchmarks. You will also be involved in interfacing and driving our design IP partners.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Engage with CMOS foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform PPA simulations on benchmark circuits.

• Work with fab partners on device and circuit level test structures, test chips, and characterization and correlation of silicon data. You will use the results of this work to influence design optimizations.

• Work with IP partners, design, and physical design teams to design advanced CMOS.

• Work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.

• Work with our commercial and product teams on Foundry and IP vendor management, track technology roadmaps, and determine appropriate technology and IP integration strategies.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, related field or equivalent practical experience.

• 8 years of experience in foundry design kits bring-up, SPICE simulations, signal/power analysis with advanced CMOS FinFET nodes.

• Experience in semiconductor/device engineering, process development, or electrical characterization of device/circuits.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering or Physics with an emphasis on semiconductor materials or device physics.

• Experience in SoC chip physical implementation.

• Understanding of analog and digital circuits such as PLLs, High Speed IO, cache and standard cell libraries in advanced CMOS FinFET nodes.