Plan and execute the verification of next-generation configurable infrastructure IPs, interconnects, and memory subsystems.

Create and enhance constrained-random verification environments using System Verilog and UVM.

Identify and write all types of coverage measures for stimulus and corner cases.

Debug tests with design engineers to deliver functionally correct blocks and subsystems.

Close coverage measures to identify verification holes and show progress towards tape-out.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

4 years of experience verifying digital logic at RTL level using System Verilog or C/C++.

Experience creating and using verification components and environments in standard verification methodology (e.g., UVM, SVA, CRV, PSS or LPDV).

Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Experience with scripting languages and software development frameworks.