Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.

Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality.

Develop diagnostic databases, software and hardware for logic and memory fail debug.

Design and implement system level test strategy.

Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT Compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

5 years of experience in DFT architecture, implementation, and verification for So Cs.

Experience in silicon bring-up, debug, or validation of DFT features.

Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).