Lead and manage functional STA team responsible for delivering system-on-chip (SoC) Static Timing Analysis.

Execute full chip timing signoff checklist, perform full chip STA, power recovery, timing ECO creation and oversee final timing signoff for SoC’s.

Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.

Drive clock tree planning and implementation for So Cs to achieve best energy, performance and area.

Collaborate with front-end, Design for Test (DFT) and Computer-aided design (CAD) teams for the design exploration and closure.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

10 years of experience with silicon implementation and chip integration.

Experience with STA sign-off constraint authoring for full-chip level, tapeout sign-off requirements, checklists, and associated automation.

3 years of experience in people management, developing employees.

Experience delivering silicon.