Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools.

Identify and write all types of coverage measures for corner-cases.

Debug tests with design engineers to deliver functionally correct design blocks.

Close coverage measures to identify verification holes and to show progress towards tape-out.

Bachelor's degree in Electrical Engineering or equivalent practical experience.

8 years of experience with creating and using verification components and environments in standard verification methodology.

Experience verifying digital logic at RTL level using System Verilog or Specman/E for FPGAs or ASICs.