About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Manage the physical design of the System on Chips (So Cs) to tape-out while collaborating with multiple team members.

• Evaluate and develop physical design methodologies and determine the System on Chip (SoC) flow.

• Work with architects and logic designers to drive architectural feasibility studies, develop timing, power, and area design goals, and explore Register Transfer Level (RTL)/design tradeoffs for physical design closure.

• Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.

• Understand architecture and design specifications with the team, and define physical design strategies to meet quality and schedule goals.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of technical experience in silicon implementation and chip integration.

• 8 years of management experience in ASIC development teams.

• Experience in engineering across physical design, implementation, and Graphic Data System (GDS) tape-out.

• Experience in floorplanning, block integration, static timing analysis, sign-off.

Preferred qualifications

• Experience in leading physical design teams working on digital designs that have taped-out and produced working silicon and delivering silicon.

• Knowledge of delivery of silicon in technology process nodes.

• Understanding of circuit design, device physics and submicron technology.

• Ability to lead cross-functional teams.