About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (So Cs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team.

• Generate, simulate, and optimize high-quality manufacturing test patterns (Stuck-at, Transition, Path Delay, and IDDQ) for Automated Test Equipment (ATE), while actively managing pattern volume and test time reduction (TTR) strategies.

• Develop and verify specialized test sequences and parametric measurement patterns to validate and characterize Analog IPs (PLLs, LDOs, ADCs) and high-speed I/Os (Ser Des, DDR, PCIe, MIPI).

• Partner closely with the Product Engineering teams to validate patterns on silicon, lead the diagnosis of ATE failures, and perform root-cause analysis to support yield learning and rapid ramp-to-production.

• Enhance DFT flows and methodologies using scripting (Tcl, Perl, Python) to automate insertion and validation processes, ensuring a "correct-by-construction" approach for future SoC.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.

• 3 years of experience in DFT specification definition architecture and insertion.

• Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.

• Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, Compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.

• Experience with Scan insertion, ATPG, Gate Level Simulations and Silicon Debug, Low Power designs, BIST, JTAG, IJTAG tools and flow.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.

• Experience with silicon bring-up, ATE pattern debug, and failure analysis (diagnosis) to support yield improvement.

• Experience in multi-voltage, and multi-clock domain So Cs.

• Familiarity with generating and validating patterns for High-Speed I/Os (HSIO) and Analog/Mixed-Signal IPs.

• Proficiency with a scripting language like Perl, Tcl or Python.