Lead the exploration of new technologies, manage silicon bring-up, and design complex Design of Experiments (DOEs).

Manage the delivery of screening solutions for high-performance computing chips developed in advanced technology nodes.

Design and implement industry-standard DFT best practices, including at-speed Transition Delay Fault (TDF), Scan, Memory Built-In Self-Test (MBIST), and memory repair for high-speed characterization.

Establish and lead pre-silicon to post-silicon correlation strategies while managing technical data exchange with foundries and IP vendors.

Design IP validation methodologies and manage the use of HVM lab equipment for complex IPs such as High-Speed Ser Des, DDR/HBM, and System-Level Testing (SLT).

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

8 years of experience in test engineering or product engineering.

Experience with 3 of the following: Design for Test (DFT), hardware development/design, analog or mixed-signal validation, chip packaging technology, post-silicon characterization, test engineering, quality and reliability (Q&R), or semiconductor manufacturing processes.