About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role you will help build System on a Chips (SoC) that power these data centers by developing and deploying comprehensive test solutions with Automatic Test Equipment (ATE) for New Product Introduction (NPI) and High Volume Manufacturing (HVM) at wafer fabs and Outsourced Assembly and Tests (OSAT). You will have an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generations of chips.

You will help to integrate SoC technologies into devices and drive ATE manufacturing testing to validate performance and screen devices. You will own all aspects of testing and work with cross-functional teams to ensure the optimal test coverage in production and high quality So Cs. You will work with various groups to develop tests, automation methodologies, develop/support internal tools for test program generation, vector tracking, test program release, etc. You will also work on releasing cost effective production test solutions into mass production.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Participate in ATE test program development for high volume manufacturing (HVM) and characterization, work with ATE Vendors and internal cross-functional teams.

• Own IP-level test development for design for testing (DFT) structural tests, functional tests, or e Fuse programming.

• Support chip-level DFT test development for Automatic Test Pattern Generation (ATPG) Scan, Memory Built-In Self Test (MBIST), logic and memory diagnostics, logic redundancy analysis, or memory repair.

• Participate in developing and executing strategies for SoC product NPI, bring-up, verification, characterization, and qualification support, including bench test, troubleshooting, test coverage optimization, new product Defective Parts per Million (DPPM) correlation, and product correlation between system and ATE.

• Provide support for production, including test program upgrade and release, volume data analytics, test time reduction and yield improvement, and Return Materials/Merchandise Authorization (RMA) analysis.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience in test engineering or product engineering.

• Experience in ASIC or SoC test development, bring-up, or debug for NPI or HVM.

• Experience with Automatic Test Equipment (ATE) (e.g., Advantest or Teradyne platforms).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• 10 years of experience in test engineering or product engineering.

• Experience with Scan/ATPG test development, especially with streaming scan network (SSN)/streaming fabric techniques, or memory BIST test development and repair scheme implementation, including BISR/BIRA.

• Experience in testing Intellectual Property (IP) such as Phase-locked Loops (PLL), Process Voltage Temperature (PVT) sensors, thermal diodes, Process Monitor Ring Oscillator (PMRO), droop detector, aging sensor, and e Fuse.

• Experience with PCIE, Double Data Rate (DDR) and HBM testing.