About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Chip Thermal Mechanical Engineer on the chip implementation team, you will address packaging mechanical and thermal issues alongside our system design teams. You will conduct early mechanical studies for emerging architectures to calculate interface stresses and warpage. Additionally, you will analyze thermal implications of various workloads and power states, focusing on the interactions between interface materials, thermal solution assemblies, and power maps. You will collaborate with system designers to create viable packaging solutions deployable in our data centers. Because our computational challenges are unique, we build our own hardware, software, and networking technologies to power Google's services. You will design the systems at the core of computing infrastructure. You will manage these systems from concepts through high-volume manufacturing, shaping the machinery that affects many users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Simulate the mechanical and thermal performance of different multi chip package devices and heatsinks.

• Develop and correlate mechanical warpage and stress modeling of the package and perform risk analysis for various package constructions.

• Manage the silicon design team and optimize chiplet layouts for optimal package performance.

• Provide thermal models of the multi-chip assembly to the system team for tray, rack, and data center thermal analysis.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 2 years of experience in thermal analysis of semiconductor chips and packages.

• Experience in structural analysis software such as: Ansys Mechanical or Abaqus.

• Experience in Computational Fluid Dynamics (CFD) and thermal analysis software such as: Flo Therm, Fluent, Icepak, Simulia, or Comsol.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience in advanced semiconductor device modeling (including multi-chip assemblies and 2.5D/3D) and co-optimize chip physical layout.

• Experience in working with cross functional teams for co-design across chip, package and system levels.

• Knowledge of capturing failure modes through simulation and estimating product lifetime.

• Familiarity with Joint Electron Device Engineering Council (JEDEC) thermal standards.

• Proficiency in applying scripts to automate thermal and mechanical simulations.