Execute high-fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on data center-class IP.

Drive Design Technology Co-Optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails).

Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.

Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what-if analysis of emerging transistor architectures.

Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

5 years of experience in physical design (RTL-to-GDS) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).

Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools.

Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction.

Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.