Lead technical evaluations of advanced process nodes and drive the strategy for custom circuits and memories/Static Random Access Memory (SRAM) to hit power-performance-area (PPA) goals.

Engage with foundry partners to receive and debug necessary collaterals for design kits, standard cells, memories, other IPs, and more.

Provide technical mentorship and guidance to circuit and physical design teams, overseeing the design and verification of custom circuits.

Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.

Collaborate with our circuits, physical design, logic design, and technology teams in advanced CMOS nodes to ensure standard cell libraries and memories/SRAMs are seamlessly integrated.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

8 years of experience in process technology, circuit design, and physical design disciplines.

Experience with advanced process technology nodes, including yield and reliability, design kit and IP collaterals, and evaluating power, performance, and area.

Experience with custom circuit/IP and physical design spaces.

Experience in transistor level design in advanced finfet nodes for standard cells and memories/SRAMs, including SPICE simulations and characterization methodology.