Develop System Verilog RTL to implement logic for ASIC products.

Create and review design microarchitecture specifications.

Develop methodology and tooling for design automation.

Work with Design Validation (DV) teams to create test plans to verify, and debug design RTL.

Work with Physical Design teams to ensure design meets physical requirements and timing closure.

PhD in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

Experience in any one domain of silicon engineering through internships, academic research, or publications (e.g., digital design basics, including synchronous and asynchronous logic, state machines, or bus protocols).

Experience in a scripting language such as Python or Perl.

Experience in Verilog or System Verilog.