Explore and evaluate different u Arch and design choices for power and performance efficient coherent and non-coherent memory systems.

Author hardware u Arch specification for next-generation coherent/non-coherent memory systems.

Analyze performance and power trade-offs.

Work with hardware design, verification, emulation and validation teams to build and test the hardware architecture.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

8 years of experience in micro-architecture and design of ASIC blocks.

Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks: Central Processing Units (CPUs), Graphics Processing Units (GPUs), Caches, Memory Management Units (MMUs) or Coherent Fabrics.

Experience in micro-architecture/design performance analysis, tools, and simulators.