Define and document the microarchitecture for complex digital designs within the TPU.

Write high-quality, performant, and power-efficient RTL code, primarily in System Verilog.

Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.

Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.

Contribute to the development and enhancement of design tools, flows, and methodologies.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

1 year of experience with register-transfer level (RTL) design using Verilog or System Verilog.