About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Lead a complex ASIC subsystem and understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.

• Define high-performance hardware/software interfaces. Write micro architecture and design specifications.

• Define efficient micro-architecture and block partitioning/interfaces and flows.

• Implement designs in System Verilog.

• Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 4 years of experience architecting networking ASICs from specification to production.

• Experience developing RTL for ASIC subsystems.

• Experience in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications

• Experience architecting networking switches, end points, and hardware offloads.

• Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.

• Experience working with software teams optimizing the hardware/software interface.

• Proficiency in TCP, IP, Ethernet, PCIe, DRAM, Network on Chip (NoC) principles and protocols.

• Proficiency in a procedural programming language (e.g., C++, Python, Go).

• Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.