About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by many users worldwide.

In this role, we are seeking an experienced packaging engineer with strong leadership and project management skills. You will work with multi-disciplinary teams throughout custom silicon development, focusing on package substrate technology, design tradeoffs, assembly evaluation, and mechanical reliability. You will develop advanced packaging solutions (2.5D/3D/3.5D) for ML chips. This involves collaborating with architects, Signal Integrity/Power Integrity (SI/PI), Thermal, and Printed Circuit Board (PCB) engineers to create high-performance packages optimized for electrical performance and assembly. You will be instrumental in incorporating advanced technologies into Google’s product design. You will be building the systems at the core of our computing infrastructure. You will manage systems from circuit design through high-volume manufacturing, directly impacting our data centers and millions of Google users worldwide.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Own the packaging architecture from early definition to New Product Introduction (NPI), acting as the primary technical lead to define chip construction boundaries during early Tensor Processing Unit (TPU) development.

• Drive packaging solutions from concept to high-volume production, managing the critical tradeoffs between manufacturing, electrical, thermal, and mechanical requirements.

• Identify and mitigate packaging risks by establishing engineering plans, conducting test vehicle experiments, and generating comprehensive assembly and reliability test plans.

• Optimize packaging solutions for yield, cost, cycle time, and quality while ensuring all designs meet the standards of Google's data center infrastructure.

• Lead project management and communication across internal engineering teams and external suppliers to ensure seamless execution from the design phase through qualification.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with package development for high volume production.

• 8 years of experience with advance packaging technology development.

Preferred qualifications

• Master's or PhD degree in Electrical Engineering.

• Experience within wafer foundries or assembly houses, demonstrating an understanding of manufacturing environments.

• Knowledge in 2.5D and 3D packaging technologies and experience driving innovation through the development of new solutions.

• Knowledge of general package assembly processes, advanced packaging materials, and reliability standards at both component and board levels.

• Ability to translate product requirements into packaging specifications by leveraging an in-depth understanding of electrical, thermal, mechanical, and reliability interactions.

• Proficiency in advanced substrate technologies and high-speed interconnects tailored for High-Performance Computing (HPC) and ML applications.