About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a CPU Front-End Design Engineer, you will take part in central processing unit (CPU) development, one of the most critical blocks of Google’s future sever System on a Chip (SoC). You will be responsible for microarchitecture, RTL design and implementation of core technology as part of Google’s data center SoC products. You will collaborate closely with architecture, verification, and physical design engineers, creating micro architectural definitions with RTL coding and running block level simulations.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).

• Define the CPU block level design document such as interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.

• Perform RTL development process (e.g., coding and debug in Verilog, System Verilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/Power Intent checks.

• Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.

• Participate in test plan and coverage analysis of the block and SoC-level verification.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience.

• 4 years of experience in full VLSI design cycle.

• Experience in VLSI development with Verilog, System Verilog, System Verilog Assertions (SVA), or VHDL, and with design verification, synthesis, timing/power analysis, and DFT.

• Experience in RTL implementation of low power designs.

Preferred qualifications

• Experience in four or more SoC cycles.

• Knowledge of modern high-performance CPU architecture and micro-architecture.