About the job

You will design and build the hardware, software, and networking technologies that power all of Google's services. You will be responsible for delivering the platform used for pre-silicon validation and verification of our custom ASICs and enable a "shift left" of Software (SW) development and complement DV in our efforts to validate the ASICs. You will create emulated hardware environments of our chip Register-Transfer Level (RTL) with custom features and models unique to emulation and enable speedup over simulation and an integrated environment before silicon availability. You will create methodology, flows, automation, and generally shepherd designs through Tapeout and beyond and own the deployment and maintenance of emulation hardware and physical infrastructure. You can be a part of this team, delivering high-value ASIC solutions to Google's infrastructure.

You will work directly with other emulation team members as well as designers, verification engineers, and software teams. You will interface with our external vendors, lab support teams, networking and security, and EDA tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You may also assist in compiling projects targeting our prototyping platforms, debugging issues in both infrastructure and design, and assisting in the hardware and lab bring up and verification of our ASIC systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Drive system bring up on emulation platforms, debug test failures and simulation/emulation mismatches.

• Bring up external I/O interfaces (e.g., PCIe, Memories, SERDES, SPI, JTAG etc.) on the emulation platforms.

• Develop and operate tests on the emulators and assist in bring-up processes from prototyping through post-silicon validation.

• Contribute to ongoing methodology and automation improvements, constantly evolving and improving emulation efficiency and value.

• Create and support emulation models from RTL and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or a related field.

• 6 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).

• Experience with coding or scripting in C, C++, Perl, TCL or Python.

• Experience with emulation systems (e.g., Ze Bu, Palladium, Veloce), compilation, debugging, performance and methodology enhancements.

Preferred qualifications

• Master's degree in Electrical Engineering or a related field.

• 10 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).

• Experience with performance analysis/debug techniques.

• Experience with simulation acceleration using transactors (DPI-C) or vendors provided accelerated verification IP.

• Knowledge of external I/O interfaces like PCIe, DDR5, HBM, SPI, or JTAG etc.

• Understanding of computer architecture including industry standard interfaces and memory subsystems.