• Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).

• Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/
  Unified Power Format (UPF) checks.

• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.

• Participate in test plan and coverage analysis of the block and ASIC-level verification.

• Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or System Verilog.

• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.