Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

Develop and maintain constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).

Create and execute verification plans and test cases. Identify and debug verification failures.

Close coverage measures to identify verification holes and to show progress towards tape-out.

Integrate any verification IP for externally developed IP into our overall verification flow.

Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience.

4 years of experience in silicon design verification using System Verilog/UVM.

Experience with SOC verification including CPUs, bus interfaces, or peripherals.

Experience in scripting languages such as Python or Perl, for automation and analysis.