Define and document the microarchitecture for digital designs within the TPU.

Develop high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in System Verilog.

Collaborate with the verification team to develop test plans, debug RTL, and ensure functional correctness.

Co-ordinate with the physical design team to meet timing, area, power, and manufacturability requirements.

Contribute to the development and enhancement of design tools, flows, and methodologies.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

2 years of experience with RTL Design.

Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

Experience optimizing designs for performance, power or area.

Experience collaborating cross-functionally with DV teams on test plan creation and execution.