• Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.

• Utilize formal property verification tools combined with formal verification closure techniques to verify properties.

• Resolve difficult to verify properties. Contribute improvements to methodologies to enhance formal verification results.

• Architect and implement reusable formal verification components.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission at Google System Infrastructure is to build the best cloud in the world for Google services and for Google Cloud customers, by solving real world business challenges of performance, cost, and scale, utilizing hardware, software, and system solutions. To better serve evolving cloud needs, Google is establishing a team in Israel to develop custom chips for servers.

In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

• 8 years of experience working on main interconnects, Direct Memory Access (DMA), controllers, and power management.

• Experience capturing design specification in a temporal assertion language such as SVA or PSL.