Lead the micro-architecture, design, and delivery of CPU subsystem infrastructure, including Clocks, Resets, Boot, and Debug/Trace logic.

Drive the integration of the CPU into the top-level SoC, managing standard interfaces (e.g., AXI, APB, CHI) and cross-functional dependencies.

Manage the execution of the design life-cycle from concept to tape-out, overseeing logic synthesis, static checks (Lint/CDC), and engineering deliverables.

Collaborate with verification, physical design, and post-silicon validation teams to ensure functionality and successful bring-up.

Mentor and manage a technical team, fostering growth and collaboration across multiple global sites.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

10 years of experience in silicon design with a focus on IP (CPU, GPU, or TPU).

Experience managing technical teams and RTL design projects to tape-out.

Experience with SoC infrastructure design (e.g., clocking, reset sequences, power intent/UPF).