Define the software architecture for multi-core embedded systems, manage memory maps, interrupt latency, and inter-processor communication (IPC).

Lead the implementation of industry-standard link training and auto-negotiation protocols for high-speed ethernet and custom interconnects.

Optimize firmware for time-to-link and power consumption, ensure the silicon stays within strict thermal envelopes during heavy AI training workloads.

Act as the primary firmware interface for the RTL design team to define register maps, APIs, and hardware or software boundaries.

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

10 years of industry experience in embedded firmware or digital signal processing (DSP) development.

Experience with high-speed I/O (HSIO), high-bandwidth transceivers, or physical layer (PHY) control software.

Experience in real-time operating systems (RTOS) and multi-threaded embedded programming.