About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the Design Verification Engineer, you will join a team focused on the functional design verification of multi-core SoC architectures. In this role, you will be responsible for maintaining data consistency across intricate memory hierarchies with exposure to interconnects and I/O subsystems. You will also define verification strategy, developing constraint-random environments and driving coverage closure.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Verify designs using verification techniques and methodologies.

• Work cross-functionally to debug failures and verify the functional correctness of the design.

• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.

Minimum qualifications

• Bachelor's degree in electrical engineering, computer engineering, computer science, a related field, or equivalent practical experience.

• 4 years of experience with design verification (e.g., System Verilog/UVM).

Preferred qualifications

• Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.

• Experience with interconnect protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).

• Experience in one or more of the following: high speed protocols, memory management, caches hierarchies, coherency, DDR/LPDDR, PCIe, packet processors.