About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Implement scalable verification framework tailored for multi-voltage SoC designs, ensuring seamless integration of design, design verification, and power methodology.

• Architect and develop infrastructure for advanced UPF (2.0/3.0) verification, focusing on complex power state transitions, and isolation across asynchronous domains.

• Implement high-performance Gate-Level Simulation (GLS) strategies, power aware flows to verify physical netlists against architectural power intent.

• Develop and integrate diagnostic hooks to transition smoothly from pre-silicon environments to silicon debug, utilizing scandump analysis and JTAG-based visibility.

• Establish best practices for low-power flows, including automation for UPF static checks, dynamic power assertions, and post-silicon failure reproduction.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience with Unified Power Format (UPF) and low-power verification methodologies, including power domain integration.

• Experience with gate-level simulation and power aware GLS, including Standard Delay Format (SDF) timing annotation and X-propagation debug.

• Experience in developing custom tools/scripts (Python/Perl/Tcl) to solve verification bottlenecks in the power-aware domain.

• Experience in SoC architectures, power management controllers, and cross-domain reset/clock sequencing.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with Low-Power Double Data Rate (LPDDR) (4/5) interface verification and power-down states in high-performance memory controllers.

• Experience with Logic Equivalence Checking (LEC) and formal verification of low-power properties.

• Experience mentoring junior engineers and collaborating with physical design and silicon validation teams.

• Proficiency in System Verilog (SV) and understanding of Advanced RISC Machines (ARM) CPU architecture (v8/v9).

• Proficiency in Scandump analysis, memory profiling, and correlating silicon behavior with gate-level models.